The Cadence® Protium™ S1 FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use. Compatible with Cadence’s Palladium® platforms and SpeedBridge® adapters, it allows for the quick and smooth transition of the system-on-chip (SoC) design from an existing emulation environment into a high-performance FPGA-based prototype.
Early Software Development
Successfully completing challenging SoC designs on time and on budget—with their ever-increasing software contents—requires starting the software-development process as early as possible. FPGA-based prototyping has long been a key technology to achieve that goal. However, growing complexities and shrinking time-to-market windows are making the bring-up of such a prototyping system increasingly painful and time-consuming.
The Protium S1 Platform addresses and solves these challenges by providing a comprehensive and productive solution for reducing the prototype bring-up from months to weeks—or even days. This speed-up is achieved by combining a hardware platform—a family of FPGA boards—with a software platform, providing a fully integrated implementation flow as well as advanced debug capabilities.
System Validation
With their high-speed, small form factor, and external system connections, FPGA-based prototyping systems are a productive solution to allow design teams to validate their IP and SoC designs within the actual system environment. With its fast design bring-up and compatibility with the SpeedBridge portfolio, the Protium S1 Platform offers distinct advantages over in-house-developed and other FPGA-based solutions.
Throughput Regressions
Using the Protium S1 platform, you can improve your product quality by running exhaustive regression tests on a high-performance, cost-effective platform.
When the majority of hardware defects in the design have been removed, users must be able to run regressions quickly, while preserving the integrity of the design under test (DUT) and the verification environment. To optimize the throughput of regression speed within budget, pair the Palladium XP Verification Computing Platform and the Palladium Z1 Enterprise Emulation Platform—including a common compile flow, identical language coverage, and the ability to re-use the Palladium verification environment—with the Protium S1 platform. This approach allows users to maximize throughput regressions, which requires less interactive hardware debugging.
The Protium S1 platform further extends the innovation within the Cadence Verification Suite—comprised of best-in-class core engines, verification fabric technologies, and solutions that increase design quality and throughput—fulfilling verification requirements for a wide variety of applications and vertical segments.