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AgendaFollowing an overview of Cadence platforms and services, and a presentation
by our guest speaker, you will have the opportunity to attend two of these
in-depth presentations and demos:
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Incisive functional
verification platform: enables a unified verification
methodology, from system to gate level integrating — simulation
(multi-mode, multi-language single kernel), static verification,
acceleration and emulation (Palladium™), code coverage and assertions.
The Incisive platform supports the functional virtual prototype (FVP)
concept and enables you to send in production system, SoCs, ASIC and
FPGA with functionality under control. |
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Encounter digital IC design
platform for ICs and SoCs: ensures convergence in timing,
power and signal integrity, down to nanometer technologies, through
silicon virtual prototype (SVP in First Encounter®), global synthesis
(RTL Compiler, GPS), NanoRoute™ super-threading graph-based router,
CeltIC™ crosstalk analysis, advanced Design for Test and diagnostic
tools (Encounter Test). |
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Virtuoso custom design platform:
leapfrog current design solutions in terms of productivity and
comprehensive analysis enabling a breakthrough in complexity whilst
improving design delays, re-spin and yield — optimisation, corner
case analysis, multi-mode simulation, automated custom layout, migration
tools, reference flows and up to 10x performance improvement. |
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Allegro system interconnect
platform: a unique co-design solution for system
interconnect, from backplane to silicon through to board and package,
based on virtual system interconnect models (VSIC), silicon design kits,
and a constraint driven board design methodology. |
Our field application engineering team will be available to address your
questions. |