Join us for this free seminar focusing on analog/mixed-signal design, implementation, and verification.
Explore the latest technologies and integrated flows from Cadence that will help you design higher performance chips and systems, more efficiently and with higher yield. Seminar highlights include new capabilities with recent and upcoming product releases (Virtuoso IC 6.1.5, Multi-Mode Simulation 10.1, Virtuoso Power System, Physical Verification System 10.1) and the many front-to-back aspects of custom design.

Dates and Locations

17 Nov 2010 - Bracknell, United Kingdom

17 Nov 2010 - Grenoble, France

18 Nov 2010 - Edinburgh, United Kingdom

18 Nov 2010 - Lausanne, Switzerland

22 Nov 2010 - Munich/Feldkirchen, Germany

23 Nov 2010 - Eindhoven, The Netherlands

24 Nov 2010 - Düsseldorf, Germany

25 Nov 2010 - Dresden, Germany

30 Nov 2010 - Milan, Italy

Who should attend?

Project managers

Design group managers

Engineering managers

Analog and RF design engineers

Mixed-signal implementation engineers

Mixed-signal verification engineers

Agenda

09:00 - 09:30	Mixed-Signal Silicon Realization
09:30 - 10:30	Boost Your Design Productivity with Virtuoso 6.1.5
10:30 - 10:45	Break
10:45 - 11:30	Automated Analog Design Verification and Optimization
11:30 - 12:15	Layout Productivity Using Advanced Layout Editing Features
12:15 - 12:45	Virtuoso Visualization and Analysis - Next-Generation Waveform Analysis
12:45 - 13:30	Lunch
13:30 - 14:30	Virtuoso Multi-Mode Simulation 10.1 - Advanced Verification Solution
14:30 - 15:00	Virtuoso Power System - Signoff Power Analysis
15:00 - 15:15	Break
15:15 - 16:00	Mixed-Signal Implementation Using Encounter and Virtuoso Technology
16:00 - 16:45	Physical Verification and Constraint Signoff Using PVS
16:45 - 17:00	Summary

Register now >>