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Scale your design process to support complex electronic systems SystemC — Powerful Modeling and Verification Learn how to reduce risks and meet your design and verification challenges: › Introduction to SystemC language › Transaction level modeling › Architecture analysis at the transaction level › SystemC simulation and debug › Advanced verification leveraging SCV library › Mixed SystemC/HDL co-verification Hands-on activities |
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Reserve your space now at:
sld@cb-distribution.nl. Fee: 150EUR per attendee |
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