Cadence Design Systems, Inc. announced the availability of the industry’s only foundry-proven IC packaging design and analysis solutions for advanced Fan-Out Wafer-Level Chip Scale Packaging (WLCSP) and 2.5D interposer-based designs. The new capabilities enable the faster multi-chip integration that is ideal for smaller, lighter and power-optimized wireless mobile devices.

This complete IC packaging design and analysis solution includes the Cadence OrbitIO Interconnect Designer, Cadence System-in-Package (SiP) Layout and Cadence Physical Verification System (PVS). This set of offerings enables multi-substrate interconnect pathway design, refinement, implementation and manufacturing verification and signoff spanning die I/O pad rings through IC package to system PCB.

The new Cadence SiP Layout WLCSP option integrated with PVS provides generic silicon wafer-based packaging methodologies previously validated by TSMC for their Integrated Fan-Out (InFO) process. Enhancements to OrbitIO Interconnect Designer strengthen 2.5D interposer package design support, providing optimal multi-die, single package interconnect integration. This enables higher performance for multi-substrate integrated devices with minimal size optimized for signal performance.

“Wireless mobility and wireless-enabled is the trend at all levels of electronic-centric products, from smartphones to cars to home appliances and beyond. They all need thin, lightweight, low-power yet high-performance devices at their core. This is the sweet spot for WLCSP, fueling its predicted explosion in adoption,” said Keith Felton, product management group director for the PCB Group at Cadence. “Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches.”