New Cadence Allegro Technology Boosts Productivity and Predictability for Silicon, SoC and System DevelopersOn 25 April 2011 Cadence introduced the latest version of its Allegro PCB and IC packaging technology, delivering new capabilities that provide a significant increase in both productivity and predictability across silicon, SoC and system development. New technologies include advanced miniaturization capabilities, uniquely integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design features, and flexible team-design enablement to address global designer productivity. The Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, thus optimizing total cost-of-ownership.
Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:
Higher functional density with a constraint-driven flow for embedded components Faster timing closure with new PCB interconnect design planning technology Fewer physical prototype iterations with concurrent team design authoring More efficient low-power design with integrated power delivery network analysis A compliant and faster implementation path with package/board-aware SoC IP Smoother collaboration among global teams with new SiP distributed co-design Flexibility through “base plus options” configurations For more details see