Imagine that your design tools for IC layout and multi-die packaging were seamlessly coupled together. And your system-level design was managed by a single hierarchical schematic that included all your package/PCB layout parasitics. Suddenly system-level LVS and verification becomes a breeze.

The Cadence Virtuoso System Design Platform lets you design seamlessly across the chip, package, and board. It eliminates the barrier between IC and package design with a formal, automated co-design and verification flow between the Virtuoso platform and Allegro and Sigrity technologies.

• Ideal for designs that integrate multiple heterogeneous ICs, including RF, analog, and digital devices
• Automatically generate Virtuoso testbench schematics from Allegro connectivity and Sigrity 3DEM models with automated “system-aware” electrical signoff
• Design across the chip, package, and board, minimizing errors and significantly improving cycle time from days to minutes