Boundary scan, as defined by the IEEE 1149.x family of standards, is a technology which enables a JTAG-enabled Integrated Circuit (IC) to relinquish control of its pins to an external agent for test purposes. The logic required to do this is included in the IC at each JTAG-enabled pin, known as a boundary scan ‘cell’. These cells are connected in series within the IC and accessed externally through a 4- or 5-pin port known as a Test Access Port, or TAP.
The TAP on each JTAG-enabled IC can be connected serially creating what is referred to as a boundary scan chain (see figure above). As each IC is a link in this chain, it is imperative that the chain’s integrity is maintained through its entirety; from where it enters the board, to where it leaves. Typically this would be on two pins of the same connector.
The XJTAG DFT Assistant for OrCAD Capture software plugin provides a level of automation in checking that one (or many) scan chain(s) on a PCB are connected and terminated correctly. Crucially, these tests are carried out at the schematic capture stage, thereby identifying errors early in the design cycle and helping to avoid costly PCB respins.
Because the software plugin is fully integrated into OrCAD Capture, most of the information needed to conduct a DFT check of a boundary scan chain, such as a netlist and BOM, can be accessed within the platform automatically. However, it is also necessary to provide some additional information that would not normally form part of an OrCAD Capture design. Specifically, a Boundary Scan Description Language (BSDL) file must be provided for each JTAG-enabled device in the design.
XJTAG DFT Assistant for OrCAD Capture is a Software Plugin for the OrCAD Capture platform, developed by XJTAG, a leader in JTAG/Boundary Scan technology. The plugin is made available free of charge and requires OrCAD Capture 17.2 or higher.