Boundary scan, as defined by the IEEE 1149.x family of standards, is a technology which enables a JTAG-enabled Integrated Circuit (IC) to relinquish control of its pins to an external agent for test purposes. The logic required to do this is included in the IC at each JTAG-enabled pin, known as a boundary scan ‘cell’. These cells are connected in series within the IC and accessed externally through a 4- or 5-pin port known as a Test Access Port, or TAP.


The XJTAG DFT Assistant for OrCAD Capture software plugin provides a level of automation in checking that one (or many) scan chain(s) on a PCB are connected and terminated correctly. Crucially, these tests are carried out at the schematic capture stage, thereby identifying errors early in the design cycle and helping to avoid costly PCB respins.


Because the software plugin is fully integrated into OrCAD Capture, most of the information needed to conduct a DFT check of a boundary scan chain, such as a netlist and BOM, can be accessed within the platform automatically. However, it is also necessary to provide some additional information that would not normally form part of an OrCAD Capture design. Specifically, a Boundary Scan Description Language (BSDL) file must be provided for each JTAG-enabled device in the design.